DLL circuit and camcorder using DLL circuit

ABSTRACT

A DLL circuit which can prevent transition to a pseudo lock state is provided. The DLL circuit includes a delay stage to which a reference clock is input and in which variable delay elements D able to change an amount of delay are connected in a plurality of stages, a phase comparator (PH Comp) which compares the phase of the reference clock to the phase of one delay signal extracted from the delay stage, a delay control circuit which performs delay control of the delay element in the delay stage on the basis of the comparison result by the phase-comparison means, and a DFF which detects a phase relationship of at least two delay signals extracted from the delay stage to discriminate a state which is not a normal lock state and controls the delay control circuit to perform state transition to the normal lock state.

NOTICE: More than one reissue application has been filed for the reissueof U.S. Pat. No. 7,019,573. The reissue applications are applicationSer. No. 12/056,927, filed on Mar. 27, 2008, and the presentapplication, which is a divisional application of application Ser. No.12/056,927.

This application is a division of application Ser. No. 12/056,927 filedMar. 27, 2008, U.S. Pat. No. Re. 43,201 E, which is a reissue of U.S.Pat. No. 7,019,573 B2 (which issued from application Ser. No. 10/847,303filed May 18, 2004).

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a DLL (Delay-Locked Loop) circuit usedfor a polyphase clock generating circuit, a multiply circuit, and thelike, particularly to a technique preventing a pseudo lock state whichis not normally locked.

2. Related Background Art

The pseudo lock state may be one of the most serious malfunctions of theDLL circuit.

In the conventional technique, as described in U.S. Pat. No. 6,259,290,there is a method in which the pseudo lock state is detected in such amanner that a plurality of pulses are generated within the 1 period of areference clock by the multiply circuit to count the number of pulses.

However, in the method described in U.S. Pat. No. 6,259,290, such acircuit as the multiply circuit, the counter, and the like is required,and there is a drawback which results in a cost increase and anelectrical power consumption increase because the circuit is enlarged.

SUMMARY OF THE INVENTION

It is an object of the invention to provide the low-cost DLL circuitwhich detects the pseudo lock state with a small-scale circuit and hashigh accuracy and high reliability.

The DLL circuit of the invention includes a delay stage to which areference clock is input and in which delay elements being able tochange an amount of delay are connected in a plurality of stages,phase-comparison means for comparing a phase of said reference clock tothe phase of one of delay signals extracted from said delay stage,controlling means for controlling the amount of delay of said delaystage on the basis of the comparison result by said phase comparingmeans, and state transition means for detecting a phase relationship ofat least two delay signals extracted from said delay stage todiscriminate a state which is not a normal lock state and forcontrolling said controlling means to transit the state to the normallock state.

Since, in the normal lock state, an output signal of the delay elementon a subsequent state side is always delayed in a delay relationship inthe delay stage in which the plurality of variable delay elements areconnected, according to the present invention, based on detection of aphase relationship between the output signals of the delay elements, itis prevented to fall into the pseudo lock state.

Depending on a type of the DLL circuit, the pseudo lock state neveroccurs in the case where the amount of delay is small, so that thecontrolling means is controlled so that the delay element becomes theminimum delay state in starting up the DLL circuit and the abnormalstate can be detected in the transition state in which the normal lockstate is disengaged to fall into the pseudo lock state.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing a first embodiment of the DLL circuitof the invention;

FIG. 2 is a block diagram of an example more specifically showing thefirst embodiment;

FIG. 3 is a timing chart of a normal lock state in a ½ periodphase-comparison DLL circuit;

FIG. 4 is a timing chart of a 1.5-period pseudo lock state in the ½period phase-comparison DLL circuit;

FIG. 5 is a timing chart of a 2.5-period pseudo lock state in the ½period phase-comparison DLL circuit;

FIG. 6 is a timing chart of a 2-period pseudo lock state in a 1 periodphase-comparison DLL circuit;

FIG. 7 is a block diagram showing a second embodiment of the DLL circuitof the invention;

FIG. 8 is a block diagram showing a third embodiment of the DLL circuitof the invention;

FIG. 9 is a timing chart of the normal lock state in the ½ periodphase-comparison DLL circuit (40-stage configuration);

FIG. 10 is a timing chart of the 1.5-period pseudo lock state in the ½period phase-comparison DLL circuit (40-stage configuration);

FIG. 11 is a timing chart of the 2.5-period pseudo lock state in the ½period phase-comparison DLL circuit (40-stage configuration);

FIG. 12A is a timing chart showing the normal lock state and FIG. 12B isa timing chart showing the pseudo lock state, in the case where a delaystage is formed by a four-stage delay element; and

FIG. 13 is a block diagram showing a fourth embodiment in which the DLLcircuit of the invention is applied to a camcorder.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Preferred embodiments of the invention will be described referring tothe accompanying drawings.

(First Embodiment)

FIG. 1 is a block diagram showing a first embodiment of the DLL circuitof the invention. As shown in FIG. 1, a ½ period phase-comparison typeof DLL circuit includes a delay stage 11 to which a reference clock CLKis input and in which variable delay elements D are connected in aplurality of stages, a phase comparator (PH Comp) 14 which compares thephase of the reference clock CLK to the phase of intermediate delayoutput Tn/2 of the delay stage 11, a low-pass filter (LPF) 13 whichreceives an output of the phase comparator 14, and a delay controlcircuit 12 which performs delay control of the delay element in thedelay stage 11. In the ½ period phase-comparison DLL circuit, twooutputs (Tm and Tn/2) which are arbitrarily delayed are connected frominside the delay stage 11 to a rising-edge trigger type of data inputflip-flop DFF 15. At this point, the output having the smaller amount ofdelay is connected to a clock input of DFF 15 and the output having thelarger amount of delay is connected to a data input of DFF 15. Theoutput of DFF 15 is connected to a reset terminal of LPF 13 and thedelay control circuit 12. LPF 13 and the delay control circuit 12 areconfigured so as to minimize delay time in a reset state. In this case,the flip-flop DFF 15 has a function of detecting the pseudo lock stateand of preventing the transition to the pseudo lock state.

FIG. 2 is the block diagram of an example more specifically showing theabove embodiment. In FIG. 2, the same components as FIG. 1 are indicatedby the same reference numerals and signs.

In FIG. 2, the ½ period phase-comparison type of DLL circuit includesthe delay stage 11 in which variable delay elements D are connected in50 stages, the phase comparator (PH Comp) 14 which compares the phase ofthe reference clock to the phase of the delay output in the 25th stage,the low-pass filter (LPF) 13 which receives the output of the phasecomparator 14, and the delay control circuit 12 which performs the delaycontrol of the delay element D. In the ½ period phase-comparison type ofDLL circuit, two outputs arbitrarily delayed are connected from insidethe delay stage 11 to the rising-edge trigger type of data inputflip-flop DFF 15. At this point, the delay output having the smalleramount of delay of the 9th stage is connected to the clock input of DFF15 and the delay output having the larger amount of delay of the 25thstage is connected to the data input of DFF 15. The output of DFF 15 isconnected to the reset terminal of LPF 13 and the delay control circuit12. LPF 13 and the delay control circuit 12 are configured so as tominimize the delay time in the reset state.

FIG. 3 shows each output wave in the normal state. In the normal state,a rising position of the delay output T25 in the 25th stage iscontrolled at the position of the ½ period of the reference clock CLK,and the rising positions of the delay output T8 in the 8th stage and thedelay output T9 in the 9th stage are located between the rising edge ofthe reference clock CLK and the rising position of the delay output inthe 25th stage. At this point, a RESET signal which is of the output ofDFF 15 becomes Low-level output.

FIG. 4 shows the pseudo lock state. In FIG. 4, the pseudo lock stateoccurs at the ½ period+the 1 period. Although the delay output in the25th stage can be seen as close as the normal lock state, actually thereference clock CLK is not the delay of the ½ period but the referenceclock CLK is the delay of the one and half periods. Thus, in the DLLcircuit of the embodiment, there is the state in which the lock occursat the amount of delay in which the period of integer multiples is addedto the phase comparison position. However, in the case of the smallamount of delay, there is no pseudo lock in the circuit configuration.The state shown in FIG. 4 is an example in which the lock occurs at the1.5 periods, the rising position of the delay output T8 in the 8th stageis located at the back of the rising position of the delay output T25,and the rising position of the delay output T9 in the 9th stage islocated in front of the rising position of the delay output T25. In thenormal lock state, the rising position of delay output T25 cannot existbetween the rising positions of the reference clock CLK and the delayoutput T9. The DFF circuit 15 detects the state in which the risingposition of delay output T25 exists between the rising positions of thereference clock CLK and the delay output T9 as the pseudo lock state,the RESET signal which is the output of the DFF becomes a High leveloutput, and the DFF circuit can cause the DLL circuit to transit to thenormal lock state by resetting the delay control circuit.

FIG. 5 shows the pseudo lock state in which the 1 period is furtheradded to the pseudo lock state shown in FIG. 4. In the pseudo lock stateof FIG. 5, both the rising positions of the delay output T8 in the 8thstage and the delay output T9 in the 9th stage are located at the backof the rising position of the delay output T25. When duty of thereference clock and the duty of each of the delay outputs are in theideal state, the DFF circuit can detect the state shown in FIG. 5 as thepseudo lock state.

A +1 period pseudo lock state of a 1 period phase-comparison type DLLcircuit will be described referring to FIG. 6 (the circuit diagram isnot shown). The 1 period phase-comparison type DLL circuit compares thephase of the reference clock CLK to the phase of the delay output in the50th stage. Therefore, in the state in which the pseudo lock occurs atthe +1 period, the delay output T25 in the 25th stage becomes equal tothe delay output T50 in the 50th stage. At this point, since the risingpositions of the delay output T8 in the 8th stage and the delay outputT9 in the 9th stage are located at the back of the rising position ofthe delay output T25, the DFF circuit can detect the state shown in FIG.6 as the pseudo lock state.

(Second Embodiment)

FIG. 7 is the block diagram showing a second embodiment of the DLLcircuit of the invention. The ½ phase-comparison type of DLL circuitincludes the delay stage 11 in which the variable delay elements D areconnected in n stages, the phase comparator (PH Comp) 14 which comparesthe phase of the reference clock CLK to the phase of the delay output inthe n/2-th stage, the low-pass filter (LPF) 13 which receives the outputof the phase comparator 14, and the delay control circuit 12 whichperforms the delay control of the delay element D. In the ½ periodphase-comparison DLL circuit, two outputs arbitrarily delayed areconnected from inside the delay stage 11 to the rising-edge trigger typeof data input flip-flop DFF 15. At this point, the output having thesmaller amount of delay is connected to the clock input of DFF 15 andthe output having the larger amount of delay is connected to the datainput of DFF 15. The output of DFF 15 is connected to one of inputs of alogic OR gate 17, and the other input of the logic OR gate 17 isconnected to the output of a startup clear circuit (SUC) 18. The outputof the logic OR gate 17 is connected to the RESET terminal of LPF 13 andthe delay control circuit 12 as the RESET signal. LPF 13 and the delaycontrol circuit 12 are configured so as to minimize the delay time inthe reset state.

The startup clear circuit (SUC) 18 is one which detects the state, suchas power-up or a power saving mode of the DLL circuit, in which circuitoperation transits from an OFF state to an ON state, and this operationallows the variable delay element D to be set to the minimum delay statein starting the DLL circuit.

Accordingly, in the DLL circuit of the embodiment, since a delay controlloop is operated from the minimum state of the delay, it is difficult totransit to the pseudo lock state having the large delay. However, evenin the case where the normal lock state is disengaged, the pseudo lockstate can be detected by detecting the phase relationship within thedelay stage with DFF.

Similarly to the example of the first embodiment shown in FIG. 2, anexample of the embodiment is also the ½ period phase-comparison type ofDLL circuit including the delay stage 11 in which the variable delayelements D are connected in 50 stages, the phase comparator (PH Comp) 14which compares the phase of the reference clock to the phase of thedelay output in the 25th stage, the low-pass filter (LPF) 13 whichreceives the output of the phase comparator 14, and the delay controlcircuit 12 which performs the delay control of the delay element D. Inthe ½ period phase-comparison DLL circuit, the two outputs arbitrarilydelayed are connected from inside the delay stage 11 to the rising-edgetrigger type of data input flip-flop DFF 15. At this point, the delayoutput having the smaller amount of delay of the 9th stage is connectedto the clock input of DFF 15 and the delay output having the largeramount of delay of the 25th stage is connected to the data input of DFF15.

In the above-described pseudo lock state, the delay stage formed by the50-stage delay element was described as the example. However, in theactual operation, since a reverse state of the phase relationship iscertainly generated in the delay stage until the normal lock statetransits to the pseudo lock state, the optimum two points in the delaystage may be selected by the number of delay stages and loop gain.

The reversal of the phase relationship of the delay signal can be alsogenerated between the delay signals of the delay elements adjacent toeach other. For example, in the case where the delay stage is formed bythe 4-stage delay element, the phase relationship is reversed within the1 period between delay signals T1 and T2 output from the delay elementsadjacent to each other as shown in FIGS. 12A and 12B. Although the delaystage formed by the small number of stages of the delay element wascited as an example, the reversal of the phase relationship can be alsogenerated in the delay stage formed by the large number of stages of thedelay element. Therefore, sometimes the phase relationship between theoutput signals of the delay elements adjacent to each other is detected.FIG. 12A shows the timing chart of the normal lock state and FIG. 12Bshows the timing chart of the pseudo lock state.

Further, in the above embodiments, although the reversal of the phaserelationship is decided by the relationship between the outputs of the25th stage and the 9th stage, the reversal of the phase relationship canbe also decided by the relationship between the outputs of the 25thstage and the stage after the 9th stage.

Therefore, even if the reference clock CLK input to the DLL circuit orthe duty of the variable delay element D is not in the ideal state, thetransition to the pseudo lock state can be prevented. The control is notlimited to the startup clear circuit, and the circuit having the sameeffect as the startup clear circuit may be used.

(Third Embodiment)

FIG. 8 is the block diagram showing a third embodiment of the DLLcircuit of the invention. In FIG. 8, the same components as FIG. 7 areindicated by the same reference numerals and signs. The third embodimentis one in which DFF 16 is provided in addition to DFF 15 in theconfiguration of the second embodiment. It will be also appreciated thatDFF 16 may be provided in the configuration of the first embodimentshown in FIG. 1.

Thus, it will be appreciated that at least one more pseudo lockdetection circuit may be provided in order to improve a detection rate.

An example of an indicator concerning selection of the delay output usedfor the detection of the pseudo lock will be described below.

As described above, in the DLL circuit, the pseudo lock state for thedesired period exists in +1 period unit. When the unlock state is in the+½ period state compared to the normal lock state, it is not clearwhether the unlocked state transits to the normal lock state or to thepseudo lock state. Therefore, for the delay output for detecting thepseudo lock state, in the ½ period phase-comparison type, when theamount of delay becomes larger than the ½ period, i.e., double thedesired amount of delay, the two outputs of the delay stage in which thephase relationship is reversed are selected. For example, in the casewhere the delay stage is formed in 50 stages, the selection of the twodelay outputs before the 50/2 step is preferable for the detection onthe pseudo lock side.

Further, in the state in which the amount of delay triples the desiredamount of delay, the outputs in which the delay relationship is reversedare selected so that the pseudo lock is securely detected in +1 period.In the delay output of the subsequent, stage, because the absolutechange in the amount of delay is larger, the output stage having theamount of delay which does not exceed the 1 period of the referenceclock even in the +1 period pseudo lock is used as a guide in one of theoutputs of the delay stage. If feasible, in the +2 period pseudo lock,the amount of delay may be also within the 1 period of the referenceclock. For example, in the case of the DLL circuit having the 50 stages,the output before the 50/2 stage is used for one of the delay outputsand the output before the 50/3 stage is used for the other delay output,or the output before the 50/5 stage is used for the other delay outputin order to satisfy the secure detection in the +2 period pseudo lock.In the case of the 1 period phase-comparison type, the output before the50/1.5 stage is used for one of the delay outputs in order not tosecurely decide the pseudo lock state before the 1.5 periods, and theamount of delay becomes larger than double the desired amount of delay,i.e., the output before the 50/2 stage may be selected for the otherdelay output in order to detect the +1 period pseudo lock, or the outputbefore the 50/3 stage may be selected for the other delay output inorder to detect the +2 period pseudo lock.

In the examples of the 50-stage DLL circuit shown in the first andsecond embodiments, the outputs of the 25th stage and the 9th stage areused as the delay output and the delay signal completely satisfying theabove-described conditions is used.

In the case where the detection is performed on the basis of the aboveconditions in the ½ period phase-comparison DLL circuit having 40-stageconfiguration, FIG. 9 shows the timing chart during the normal lockstate, FIG. 10 shows the timing chart of the +1 period pseudo lockstate, and FIG. 11 shows the timing chart of the +2 period pseudo lockstate. In this case it is possible to satisfy the above conditions byusing the delay output of the 7th stage and the delay output of the 14thstage or the delay output of the 20th stage.

Even if these conditions are completely satisfied, since the delayrelationship is always reversed in the process of the transition to thepseudo lock, the detection can be performed by selecting the delayoutputs on the assumption that the amount of delay becomes larger thanthe ½ period to the desired amount of delay. Alternatively, theplurality of detection circuits such as the combination detecting the +1period pseudo lock state, the combination detecting the +2 period pseudolock state, and the combination detecting the +3 period pseudo lockstate can be provided to improve the detection rate.

Although the output of the delay element input to the data inputterminal of the DFF corresponds to the output of the delay element inputto the phase comparator in the above embodiment, it is not alwaysnecessary that the output of the delay element input to the data inputterminal of the DFF corresponds to the output of the delay element inputto the phase comparator, and it will be appreciated that the output ofthe delay element input to the data input terminal of the DFF and theoutput of the delay element input to the phase comparator are outputfrom the individual variable delay element.

As described above, in the second and third embodiments, the transitionto the pseudo lock can be prevented in such a manner that the flip-flopcircuit DFF and the startup clear circuit SUC are added to the DLL basiccircuit, the delay is started from the minimum state, and the before-andafter before-and-after phase relationship in the delay stage isdetected. When the power saving mode signal exists, the power saving canbe achieved only by the flip-flop circuit with setting function, so thata low-cost, high-reliability DLL circuit can be provided. Further, inthe first to third embodiments, since it is not necessary to change thedelay stage and the input reference clock, excessive delay is nevergenerated and the DLL circuit can be implemented with high accuracy.

(Fourth Embodiment)

One example of the cases in which the DLL circuit of the invention isapplied to a camcorder will be described in detail below referring toFIG. 13.

FIG. 13 is the block diagram showing the case in which the DLL circuitof the invention is applied to the camcorder. The lens designated by thenumeral 21 includes a focus lens 21A which adjusts a focus with a takinglens, a zoom lens 21B which performs a zoom operation, and an imaginglens 21C.

The numeral 22 designates an iris, the numeral 23 designates asolid-state image sensing device which photoelectrically converts asubject image imaged on an imaging area into an electric imaging signal,and the numeral 24 designates a sample hold circuit (S/H circuit). TheS/H circuit 24 performs sample hold of the imaging signal output fromthe solid-state image sensing device, amplifies the level of the imagingsignal, and outputs a video signal.

The numeral 25 designates a process circuit which performs predeterminedprocessing such as gamma correction, color separation, and blanking tothe video signal output from the sample hold circuit 24 and outputs aluminance signal Y and a chroma signal C. In a color signal correctioncircuit 31, the corrections of white balance and color balance areperformed to the chroma signal C output from the process circuit 25, andthe chroma signal C after the corrections is output as color differencesignals R-Y and B-Y. The luminance signal Y output from the processcircuit 25 and the color difference signals R-Y and B-Y output from thecolor signal correction circuit 31 are modulated by an encoder circuit(ENC circuit) 34 and output as a standard television signal. Then, thestandard television signal is supplied to a video recorder (not shown)or a monitor EVF such as an electronic view finder (not shown).

The numeral 26 designates an iris control circuit which controls an irisdrive circuit 27 on the basis of the video signal supplied from the S/Hcircuit 24 and automatically controls an ig meter in order to control anumerical aperture of the iris 22 so that the level of the video signalbecomes a predetermined value having a certain level. The numerals 33and 34 designate a band-pass filter (BPF) which extracts ahigh-frequency component required to detect a focal point in the videosignal output from the sample hold circuit 24, and the band-pass filters33 and 34 restrict a different band. The signals output from the firstband-pass filter (BPF1) 33 and the second band-pass filter (BPF2) 34 aregated by a focus gate frame signal in a gate circuit 35, respectively,peak values of the signals are detected and held by a peak detectingcircuit 36, and the signals are input to a logical control circuit 37.

The signals are referred to as focal voltage, and the focusing isperformed by the focal voltage.

The numeral 38 designates a focus encoder which detects a moved positionof the focus lens 21A, the numeral 39 designates a zoom encoder whichdetects a focal distance of the zoom lens 21B, and the numeral 40designates an iris encoder which detects the numerical aperture of theiris 22. The detection values of these encoders are supplied to thelogical control circuit 37.

The logical control circuit 37 detects and adjusts the focal point tothe subject on the basis of the video signal corresponding to an areaset to detection of the focal point. Namely, the logical control circuit37 takes in information on the peak values of the high-frequencycomponents supplied from the band-pass filters 33 and 34, and suppliescontrol signals such as a rotational direction, rotational speed,rotation and stop of a focus motor 30 to the focus drive circuit 29 andcontrols the control signals in order to drive the focus lens 21A to theposition where the peak value of the high-frequency component becomesthe maximum.

The DLL circuit of the invention is provided in a timing generator (TG)50 and used so as to drive the photoelectric conversion device 23 and tofinely adjust drive timing of the S/H circuit 24 and the like.

As described above, according to the invention, the transition to thepseudo lock can be prevented. Further, since the delay can be startedfrom the minimum state by providing the means for controlling the amountof delay so as to minimize the amount of delay during the startup of theDLL circuit in power-up and the power saving mode, the transition to thepseudo lock state becomes more difficult.

1. A DLL circuit comprising: a delay stage to which a reference clock isinput and in which delay elements able to change an amount of delay areconnected in a plurality of stages; phase-comparison means for comparinga phase of the reference clock to the phase of one of delay signalsextracted from said delay stage; controlling means for controlling theamount of delay of said delay stage on the basis of the comparisonresult by said phase-comparison means; state transition means fordetecting a phase relationship of at least two delay signals extractedfrom said delay stage to discriminate a state which is not a normal lockstate and for controlling said controlling means to transit the state tothe normal lock state; and means for controlling said controlling meansso as to minimize the amount of delay in starting up the DLL circuit. 2.A DLL circuit according to claim 1, wherein reversal of a delayrelationship of the phase of one of the delay signals to the phase ofanother delay signal is detected in detection of a phase relationship ofsaid state transition means.
 3. A DLL circuit according to claim 1,wherein said state transition means is an edge trigger type of datainput flip-flop circuit, a delay signal of a previous stage having asmaller amount of delay extracted from said delay stage is connected toa clock input of said flip-flop circuit, and the delay signal of asubsequent stage having a larger amount of delay is connected to a datainput of said flip-flop circuit.
 4. A camcorder having a DLL circuitaccording to claim
 1. 5. A DLL circuit comprising: a delay stage towhich a reference clock is input and in which delay elements able tochange an amount of delay are connected in a plurality of stages;phase-comparison means for comparing a phase of the reference clock tothe phase of one of delay signals extracted from said delay stage;controlling means for controlling the amount of delay of said delaystage on the basis of the comparison result by said phase-comparisonmeans; and state transition means for controlling said controlling meansso that the amount of delay of said delay stage is minimized in startingup the DLL circuit, for detecting a phase relationship of at least twodelay signals extracted from said delay stage to discriminate a statewhich is not a normal lock state except the start-up of the DLL circuitand for controlling said controlling means to transit the state to thenormal lock state.
 6. A DLL circuit comprising: a delay stage to which areference clock is input and in which delay elements able to change anamount of delay are connected in a plurality of stages; phase-comparisonmeans for comparing a phase of the reference clock to the phase of oneof delay signals extracted from said delay stage; controlling means forcontrolling the amount of delay of said delay stage on the basis of thecomparison result by said phase-comparison means; and a plurality ofstate transition means for detecting a phase relationship of at leasttwo delay signals extracted from said delay stage to discriminate astate which is not a normal lock state and for controlling saidcontrolling means to transit the state to the normal lock state.
 7. Acamera comprising a DLL circuit, the DLL circuit comprising: a delaystage inputting a reference clock, and comprising a plurality of delayelements connected to form a plurality of stages, wherein a delay timeof each delay element is controllable; phase-comparison means forcomparing phases of clocks selected from among the reference clock anddelayed clocks outputted from the delay elements; first controllingmeans for controlling the delay time of the delay stage on the basis ofthe comparison result by the phase-comparison means; state transitionmeans for detecting a phase relationship of clocks to determine as towhether or not a state of the DLL circuit is a normal lock state; secondcontrolling means for controlling said first controlling means so as tominimize the delay time in starting up the DLL circuit.
 8. A cameraaccording to claim 7, wherein said state transition means detects, asthe phase relationship, a reversal of a delay relationship of the phaseof one of the clocks to the phase of another of the clocks.
 9. A cameraaccording to claim 7, wherein said state transition means comprises anedge trigger type data input flip-flop circuit, inputs from a clockinput of the flip-flop circuit a delay signal of a smaller delay amountfrom a former stage, and inputs from a data input of the flip-flopcircuit a delay signal of a larger delay amount from a latter stage. 10.A camera according to claim 7, wherein a plurality of said statetransition means are provided in the DLL circuit.
 11. A DLL circuitcomprising: a delay stage inputting a reference clock, and comprising aplurality of delay elements connected in a plurality of stages whichoutput delay clocks, wherein a delay time of each delay element iscontrollable; phase-comparison means for comparing phases of clocksselected from among the reference clock and delay clocks outputted fromthe delay elements; control means for controlling the delay time of saiddelay stage on the basis of the comparison result by saidphase-comparison means; and state transition means for detecting a phaserelationship of delay clocks to determine whether or not a state of theDLL circuit is in a normal lock state, wherein said control means isreset in either case of when said state transition means determines thatthe DLL circuit is not in the normal lock state or when starting up theDLL circuit, the delay time of said delay stage is minimized through theresetting of the control means, and said state transition means detects,as the phase relationship, a reversal of a delay relationship of thephase of one of the delay clocks to the phase of another of the delayclocks.
 12. A DLL circuit according to claim 11, wherein said statetransition means comprises an edge trigger type data input flip-flopcircuit, inputs from a clock input of the flip-flop circuit a delayclock from a first stage in said delay stage, and inputs from a datainput of the flip-flop circuit a delay clock from a second stagepositioned downstream of the first stage in said delay stage.
 13. A DLLcircuit according to claim 11, wherein a plurality of said statetransition means are provided.
 14. A camera comprising a DLL circuitaccording to claim 11.